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om .c based on 1M x 4Bank x16 I/O 64Mb Synchronous DRAM 4U et Document Title he aS Revision History at .D w w w
4Bank x 1M x 16bits Synchronous DRAM
Revision No. History First Version Release 1.0 1. Changed tOH: 2.0 --> 2.5 [tCK = 7 & 7.5 (CL3) Product] 1.1 1. Changed Input High/Low Voltage (Page 08) 2. Changed DC characteristics (Page 09) - IDD2NS: 18mA -> 15mA - IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA [Speed 200 / 166 / 143 / 133MHz] 3. Changed Clock High / Low pulse width Time (Page 11) 4. Changed tAC Time (Page11) 5. Changed tRRD Time (Page12)
Draft Date
Remark
Nov. 2004
1.2
1.3 1.4 1.5
m o .c U t4 e e h S ta a .D w w w
Dec. 2004 1. Corrected Revision No.: 2.0 -> 1.1 2. Deleted Remark at Revision History 3. Corrected AC OPERATING CONDITION - CL 50pF -> 30pF 4. Changed DC OPERATING CONDITION - VIH MAX VDDQ+2.0 -> VDDQ+0.3 and Typ 3.3 -> 3.0 - VIL MIN VSSQ-2.0 -> -0.3 Dec. 2004 1. Modified note for Super Low Power in ORDERING INFORMATION 1. Corrected PIN ASSIGNMENT A12 to NC Jan. 2005 Jan. 2005 1. Corrected comments for overshoot and undershoot Feb. 2005
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 / Feb. 2005 1
om .c 4U et he aS at .D w w w
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of 1,048,576x16. HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
* * * * * * Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM * Internal four banks operation * Burst Read Single Write operation Programmable CAS Latency; 2, 3 Clocks * * * Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No. HY57V641620E(L/S)T(P)-5I HY57V641620E(L/S)T(P)-6I HY57V641620E(L/S)T(P)-7I HY57V641620E(L/S)T(P)-HI Clock Frequency 200MHz 166MHz 143MHz 133MHz 4Banks x 1Mbits x16 LVTTL 54 Pin TSOPII Organization Interface Package
Note: 1. HY57V641620ET-xI Series: Normal power, Leaded. 2. HY57V641620ELT-xI Series: Low power, Leaded. 3. HY57V641620EST-xI Series: Super Low power, Leaded. 4. HY57V641620ETP-xI Series: Normal power, Lead Free. 5. HY57V641620ELTP-xI Series: Low power, Lead Free. 6. HY57V641620ESTP-xI Series: Super Low Power, Lead Free
Rev. 1.5 / Feb. 2005
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
PIN ASSIGNMENTS
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch
Rev. 1.5 / Feb. 2005
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
PIN DESCRIPTION
SYMBOL CLK TYPE Clock DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7 Auto-precharge flag: A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
CKE CS BA0, BA1
Clock Enable Chip Select Bank Address
A0 ~ A11
Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input / Output Power Supply / Ground Data Output Power / Ground No Connection
RAS, CAS, WE
UDQM, LDQM DQ0 ~ DQ15 VDD / VSS VDDQ / VSSQ NC
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row Counter
CLK CKE
State Machine Row Active
1Mx16 BANK 3
Row Pre Decoder
1Mx16 BANK 2 1Mx16 BANK 1 1Mx16 BANK 0
DQ0
I/O Buffer & Logic Sense AMP & I/O Gate
X-Decoder X-Decoder X-Decoder X-Decoder
CS RAS CAS
Refresh
Memory Cell Array
Column Active
WE U/LDQM
Column Pre Decoder
DQ15
Y-Decoder
Bank Select
Column Add Counter
A0 A1
Address Buffers
Address Register
Burst Counter
A11
BA1 BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature / Time Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Rating -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 / 10
oC
Unit
oC o
C
V V mA W / Sec
DC OPERATING CONDITION (TA= -40 to 85oC)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1, 2 1, 3
Note: 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA= -40 to 85 oC, VDD=3.30.3V, VSS=0V)
Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note: 1.
Vtt=1.4V
Symbol VIH / VIL Vtrip tR / tF Voutref CL
Value 2.4 / 0.4 1.4 1 1.4 30
Vtt=1.4V
Unit V V ns V pF
Note
1
RT=500
RT=50
Output
Output
30pF
Z0 = 50
30pF
DC Output Load Circuit
AC Output Load Circuit
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
CAPACITANCE (TA= -40 to 85 oC, f=1MHz, VDD=3.3V)
Parameter CLK Input capacitance A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM DQ0 ~ DQ15 Pin Symbol CI1 CI2 CI/O Min 2.0 2.5 3.0 Max 4.0 5.0 5.5 Unit pF pF pF
Data input / output capacitance
DC CHARACTERRISTICS I (TA= -40 to 85oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL Min -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA
Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6
Rev. 1.5 / Feb. 2005
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
DC CHARACTERISTICS II (TA= -40 to 85oC)
Parameter Symbol Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRC tRC(min), All banks active Normal Self Refresh Current IDD6 CKE 0.2V Low power Super Low power Speed 5 6 7 H Unit Note
Operating Current
IDD1
120 110 100 100 2 2
mA mA mA
1
Precharge Standby Cur- IDD2P rent IDD2PS in Power Down Mode
Precharge Standby Cur- IDD2N rent in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS
18 mA 15 3 3
mA
Active Standby Current in Non Power Down Mode
IDD3N
40 mA 35 120 110 100 100 170 160 150 150 1 400 300 mA mA mA 3 uA uA 3, 4 1 2
IDD3NS Burst Mode Operating Current Auto Refresh Current IDD4 IDD5
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V641620ET(P)-xI Series: Normal Power HY57V641620ELT(P)-xI Series: Low Power HY57V641620EST(P)-xI Series: Super Low Power
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter CL = 3 CL = 2 Symbol tCK3 tCK2 tCHW tCLW CL = 3 CL = 2 tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH 5 Min 5.0 10 1.75 1.75 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 Max 1000 4.5 6.0 4.5 6.0 Min 6.0 10 2.0 2.0 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 6 Max 1000 5.4 6.0 5.4 6.0 Min 7.0 10 2.0 2.0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 7 Max 1000 5.4 6.0 5.4 6.0 Min 7.5 10 2.5 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 H Max 1000 5.4 6.0 5.4 6.0 Unit Note
System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 2
CLK to Data Output in Low-Z Time tOLZ CLK to Data Output in High-Z Time CL = 3 CL = 2 tOHZ3 tOHZ2
Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
Rev. 1.5 / Feb. 2005
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter RAS Cycle Time RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Operation Symbol tRC 5 Min 55 55 15 38.7 15 10 1 0 2 Max 100K Min 60 60 18 42 18 12 1 0 2 6 Max 100K Min 63 63 20 42 20 14 1 0 2 tDPL + tRP 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1 7 Max 100K Min 63 63 20 42 20 15 1 0 2 H Max 120K Unit Note ns ns ns ns ns ns CLK CLK CLK
Auto Refresh tRRC tRCD tRAS tRP tRRD tCCD
Write Command to Data-In DetWTL lay Data-in to Precharge Command tDPL Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data CL = 3 Output High-Z CL = 2 Power Down Exit Time Self Refresh Exit Time Refresh Time tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF
Note: 1. A new command can be given tRRC after self refresh exit.
Rev. 1.5 / Feb. 2005
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read Read with charge Write Write with charge AutopreH X L H L L X CA AutopreH X L H L H X CA CKEn-1 H H H CKEn X X X CS L H L L RAS L X H L CAS L X H H WE L X H H DQM X X X RA L H L H H H X L L H L X X L X X X A9 ball High (Other balls OP code) MRS Mode V V ADDR A10/AP OP code X V BA Note
Precharge All Banks Precharge Bank Burst Stop DQM Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit selected
X V
H H H H H L
X
L
H X
H
L
X V
H X L H
L L L H L H L H L H L
L L L X H X H X H X V X
L L L X H X H X H X V
H L H X H X H X H X V
X X X X
X
Entry Precharge power down Exit
H
L
X X X
L
H
Clock Suspend
Entry Exit
H L
L H
X X
X
Rev. 1.5 / Feb. 2005
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Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960)
0.150(0.0059) 0.050(0.0020)
1.194(0.0470) 0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016) 0.300(0.012)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 1.5 / Feb. 2005
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